The present invention relates to a semiconductor apparatus and a diagnostic test method and, for example, relates to a technique for executing a diagnostic test of a processing circuit that accesses a storage circuit.
In a semiconductor apparatus that supports the functional safety, a mechanism for making a diagnosis whether a circuit is operating correctly or not at regular intervals is required. In the case where a circuit to be diagnosed is a CPU (Central Processing Unit) in a small logic scale, whether the CPU is operating correctly can be diagnosed by implementing lockstep. The lockstep is a mechanism that mounts a plurality of the same CPUs on a semiconductor apparatus and determines whether all of the CPUs operate in the same way, and thereby diagnoses whether the circuit is operating correctly. Thus, in the case where a circuit to be diagnosed is a CPU in a large logic scale, the number of CPUs mounted increases, which raises a problem that the lockstep cannot be implemented due to the constraints on the circuit area.
Besides the lockstep, another mechanism for making a diagnosis whether a circuit is operating correctly or not is a self-test by software. However, the self-test by software has a problem that development costs of software are generally high. Therefore, as disclosed in Japanese Unexamined Patent Publication No. 2010-140219, BIST (Built In Self Test) is employed as a mechanism for making a diagnosis whether a circuit is operating correctly or not.
However, there is a problem that, in the case where a scan test like BIST is executed, data stored in a storage circuit to which a test target processing circuit accesses is overwritten. For example, after executing the scan test, it is necessary to reset the test target processing circuit in order to resume the operation of the circuit and, in some cases, the processing circuit initializes the data stored in the storage circuit due to this reset. Further, in some cases, when the scan test is executed, unintended writing of data is done from the test target processing circuit to the storage circuit, for example. Particularly, in the case where the storage circuit is a cache memory, if the data is initialized, cache errors occur frequently when the processing circuit resumes processing after the scan test is executed, which can cause the degradation of performance.